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tlc320ad91c data manual stereo audio codec slas185a october 1998 printed on recycled paper
important notice texas instruments and its subsidiaries (ti) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. ti warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with ti?s standard warranty. testing and other quality control techniques are utilized to the extent ti deems necessary to support this warranty. specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage (?critical applications?). ti semiconductor products are not designed, authorized, or warranted to be suitable for use in life-support devices or systems or other critical applications. inclusion of ti products in such applications is understood to be fully at the customer?s risk. in order to minimize risks associated with the customer?s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. ti assumes no liability for applications assistance or customer product design. ti does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of ti covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. ti?s publication of information regarding any third party?s products or services does not constitute ti?s approval, warranty or endorsement thereof. copyright ? 1998, texas instruments incorporated
iii contents section title page 1 introduction 1?1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 features 1 ? 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 functional block diagram 1 ? 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 terminal assignments 1 ? 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 ordering information 1 ? 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 terminal functions 1 ? 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 functional description 2?1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 analog input/output ports 2 ? 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.1 analog outputs 2 ? 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.2 analog inputs 2 ? 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 digital interface 2 ? 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.1 ac-link signal definitions 2 ? 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.2 protocol 2 ? 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.3 frame contents 2 ? 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.4 ac-link low-power mode 2 ? 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 software interface 2 ? 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.1 reset register (index 00h) 2 ? 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.2 play master volume stereo and mono registers (index 02h and 06h) 2 ? 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.3 pcbeep volume register (index 0ah) 2 ? 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.4 analog mixer input gain registers (index 0ch ? 18h) 2 ? 11 . . . . . . . . . . . . . . . . 2.3.5 record select control register (index 1ah) 2 ? 11 . . . . . . . . . . . . . . . . . . . . . . . . 2.3.6 record gain register (index 1ch) 2 ? 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.7 general-purpose register (index 20h) 2 ? 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.8 power-down control/status register (index 26h) 2 ? 12 . . . . . . . . . . . . . . . . . . . 2.3.9 reserved registers (index 28h ? 59h) 2 ? 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.10 vendor reserved registers (index 5ah ? 7ah) 2 ? 13 . . . . . . . . . . . . . . . . . . . . . 2.3.11 vendor id registers (index 7ch ? 7eh) 2 ? 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4 clocking 2 ? 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5 resetting the tlc320ad91c 2 ? 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5.1 cold reset 2 ? 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5.2 warm reset 2 ? 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5.3 reset from test mode 2 ? 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6 microphone input programmable gain amplifier 2 ? 16 . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7 power-down management 2 ? 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.8 mixer functions 2 ? 18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iv 3 specifications 3 ? 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 absolute maximum ratings over operating free-air temperature range 3 ? 1 . . . . . 3.2 recommended operating conditions 3 ? 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.1 static digital specifications, t a = 25 c, av dd1 = av dd2 = dv dd1 = 5 v + 0.5 v, dv dd2 = 3.3 v + 0.3 v 3 ? 1 . . . . . . . 3.3 electrical characteristics 3 ? 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.1 analog-to-digital converter, t a = 25 c, av dd1 = av dd2 = dv dd1 = dv dd2 = 5 v + 0.5 v, f s = 48 khz, gain settings at 0 db, input = 1 v rms sine wave at 1 khz 3 ? 2 . . 3.3.2 digital-to-analog converter, t a = 25 c, av dd1 = av dd2 = dv dd1 = dv dd2 = 5 v + 0.5 v, f s = 48 khz, gain settings at 0 db 3 ? 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.3 reference specifications, t a = 25 c, av dd1 = av dd2 = dv dd1 = dv dd2 = 5 v + 0.5 v, f s = 48 khz 3 ? 3 . . . . . . . . . 3.3.4 circuit specifications, t a = 25 c, av dd1 = av dd2 = dv dd1 = dv dd2 = 5 v + 0.5 v, f s = 48 khz, for gain settings at 0 db, input = 1 v rms sine wave at 1 khz 3 ? 4 . . . . . . . . . 3.4 timing requirements 3 ? 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.1 device timing requirements, t a = 25 c, av dd1 = av dd2 = dv dd1 = dv dd2 = 5 v + 0.5 v, f s = 48 khz, for gain settings at 0 db, input = 1 v rms sine wave at 1 khz 3 ? 5 . . . . . . . . . 3.4.2 ate test mode timing requirements, t a = 25 c, av dd = dv dd = 5 v dc, av ss = dv ss = 0 v, 50-pf external load 3 ? 6 . . . . . 4 parameter measurement information 4 ? 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 application information/system usage 5 ? 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1 software driver support for the texas instruments tlc320ad91c stereo codec 5 ? 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2 the texas instruments tlc320ad91c connected to an ac ? 97 compliant digital controller 5 ? 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3 testability 5 ? 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.1 activating the test modes 5 ? 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.2 test mode functions ? ate in circuit test mode 5 ? 2 . . . . . . . . . . . . . . . . . . . . . appendix a mechanical data a ? 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
v list of illustrations figure title page 2 ? 1 ac-link bidirectional audio frame (as implemented) 2 ? 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ? 2 ac-link signals 2 ? 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ? 3 ac-link protocol 2 ? 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ? 4 tlc320ad91c power-down mode timing 2 ? 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ? 5 crystal configuration 2 ? 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ? 6 external oscillator configuration 2 ? 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ? 7 microphone programmable gain amplifier with two electret microphones 2 ? 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ? 8 tlc320ad91c power-down/ power-up flow example 2 ? 17 . . . . . . . . . . . . . . . . . . . . . . . . 2 ? 9 tlc320ad91c power-down/power-up flow example with analog still alive 2 ? 17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ? 1 ac-link low-power mode timing 4 ? 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ? 2 clock timing 4 ? 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ? 3 data setup and hold timing 4 ? 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ? 4 signal rise and fall timing 4 ? 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ? 5 cold reset timing 4 ? 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ? 6 warm reset timing 4 ? 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ? 7 ate test mode timing 4 ? 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ? 1 system diagram 5 ? 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ? 2 connection to an ac ? 97 digital controller 5 ? 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
vi list of tables table title page 2 ? 1 ac-link signal definitions 2 ? 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ? 2 sdout frame contents (driven by audio controller) 2 ? 5 . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ? 3 sdata_in frame contents 2 ? 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ? 4 tlc320ad91c register definitions 2 ? 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ? 5 reset register id bit definitions 2 ? 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ? 6 play master volume register definitions 2 ? 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ? 7 pcbeep register definitions 2 ? 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ? 8 analog mixer input gain register definitions 2 ? 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ? 9 right record select control register definitions 2 ? 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ? 10 left record select control register definitions 2 ? 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ? 11 record gain register definitions 2 ? 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ? 12 general-purpose register definitions 2 ? 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ? 13 power-down control/status register bits d0 ? d3 definitions 2 ? 13 . . . . . . . . . . . . . . . . . . 2 ? 14 power-down control/status register bits d8 ? d13 definitions 2 ? 13 . . . . . . . . . . . . . . . . . 2 ? 15 power-down modes 2 ? 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ? 16 tlc320ad91c mixer functions 2 ? 18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1 ? 1 1 introduction the tlc320ad91c is designed to be 100% compliant with the audio codec ? 97 (ac ? 97) standard specification. the codec is designed to be controlled by a digital controller. the two fixed 48-khz sample rate dacs support a stereo pcm output channel that contains a mix, determined by the codec controller, of all digital audio sources, including an internal synthesizer, and any other digital sources. the output of these dacs is mixed with additional analog sources and sent to the independently-controlled linop output. for a speakerphone, the monop output delivers either mic only or a mono mix of sources to a telephony subsystem. the adc path supports two channels of fixed 48-khz sample rate inputs. the standard stereo pcm input channel supports the record of any mono or stereo source, or a mix of sources. 1.1 features ? compliant with audio codec (ac) ? 97 specification ? serial (ac-link) interface port ? full-duplex codec with 18-bit resolution adc and dac ? 48-khz sample rate ? multiple stereo input mixer: line, cd, vid, and aux ? line level mono inputs for speakerphone and beep ? mono mic input switchable from two different sources ? very low interchannel crosstalk preserves stereo fidelity ? adc and dac total harmonic distortion met for full-scale (0.9 v rms ) levels ? stereo line level output plus mono output for speakerphone ? mono and stereo volume control ? power management support (power down mode) ? interfaces to 5-v or 3.3-v digital controller ? operates from 3.3-v or 5.5-v power supply ? standard 48-pin tqfp package ? tone free adc and dac in pc environment
1 ? 2 1.2 functional block diagram ac ? 97 digital interface 64 x 16 registers ac-link 2-channel adc 2-channel dac sync reset bitclk sdatin sdout adc_r gain ? gain ? gain ? gain ? gain ? gain ? gain ? gain ? pcbeep phone 20 db mic1 mic2 mic_in gain ? gain ? gain ? mic_in phone liner cdr monop liner linel cdr cdl vidr vidl auxr auxl lineoutr lineoutl linel cdl vidr vidl auxr auxl 12 to ? 34.5 db @ 1.5 db/step 0 to ? 46.5 db @ 1.5 db/step ? gain = gain, attenuate, mute adc_l
1 ? 3 1.3 terminal assignments 14 15 lineoutr lineoutl nc nc cap2 cap1 afilt2 afilt1 refout ref av ss1 av dd1 36 35 34 33 32 31 30 29 28 27 26 25 16 1 2 3 4 5 6 7 8 9 10 11 12 dv dd1 xtlin xtlout dv ss1 sdout bitclk dv ss2 sdatin dv dd2 sync reset pcbeep 17 18 19 20 nc nc nc 47 46 45 44 43 48 42 nc nc nc nc nc mic2 linel liner auxr vidr cdl cdgnd cdr mic1 40 39 38 41 21 22 23 24 37 13 monop nc auxl pt package (top view) av dd2 vidl phone av ss2 nc ? no internal connection 1.4 ordering information package t a chip carrier (pt) 0 c to 70 c TLC320AD91CPT
1 ? 4 1.5 terminal functions terminal i/o description name no. i/o description afilt1 29 i reference input/output. pulls to midrail if not driven. afilt2 30 o on-chip generated supply independent reference output auxl 14 i auxiliary input left channel from internal connector. auxl is used for upgrade synthesizer or other source. auxr 15 i auxiliary input right channel from internal connector. auxr is used for upgrade synthesizer or other source. av dd1 25 i analog 5-v supply voltage av dd2 38 i analog 5-v supply voltage av ss1 26 i analog ground av ss2 42 i analog ground bitclk 6 o 12.288-mhz serial data clock cdgnd 19 i cd audio analog ground (for pseudo-differential inputs) from cdrom. cap1 31 o buffered afilt1. used as adc reference. cap2 32 o buffered afilt1. used as dac reference. cdl 18 i cd audio left channel from cdrom ? pseudo-differential input cdr 20 i cd audio right channel from cdrom ? pseudo-differential input dv dd1 1 i digital 5-v supply voltage dv dd2 9 i digital 5-v or 3.3-v supply voltage dv ss1 4 i digital ground dv ss2 7 i digital ground linel 23 i line in left channel. linel connects to line-in jack. will drive 600- ? load. liner 24 i line in right channel. liner connects to line-in jack. will drive 600- ? load. lineoutl 35 o line output left channel to output jack. lineoutr 36 o line output right channel to output jack. mic1 21 i desktop (primary) microphone input. mic1 connects to the microphone jack. mic2 22 i second microphone input. mic2 connects to the headset microphone jack. monop 37 o mono output. monop is generally used to drive a telephony subsystem (and/or speakerphone card). will drive 600- ? load. pcbeep 12 i pc speaker beep pass through. pcbeep connects to the output of the pc speaker. phone 13 i telephony subsystem speakerphone input (dlp ? down line phone) ref 27 o reference voltage refout 28 o reference voltage. provides a 5-ma drive to bias microphones. nc 33,34, 39 ? 41, 43 ? 48 no connect reset 11 i master hardware reset sdatin 8 o serial time-division-multiplexed tlc320ad91c output stream sdout 5 i serial time-division-multiplexed tlc320ad91c input stream sync 10 i 48-khz fixed sample sync signal
1 ? 5 1.5 terminal functions (continued) terminal i/o description name no. i/o description vidl 16 i video audio left channel. vidl connects to a tv tuner or video camera (typically an internal connector). vidr 17 i video audio right channel. vidr connects to a tv tuner or video camera (typically an internal connector). xtlin 2 i 24.576-mhz crystal xtlout 3 o 24.576-mhz crystal
1 ? 6
2 ? 1 2 functional description 2.1 analog input/output ports 2.1.1 analog outputs the tlc320ad91c mixer generates the following two distinct audio outputs: ? a stereo mix of all sources for output to the speakers, headset, and linop output ? a mono, mic only, or mix of all sources (except phone and pcbeep) for speakerphone output (monop) 2.1.2 analog inputs the tlc320ad91c supports all analog audio inputs required by the audio codec ? 97 (ac ? 97) specification. specifically, the device supports the playback and record of all digital and analog sources likely to be present in pcs. these sources include the following: ? system audio: digital pcm input and output for business, games, and multimedia ? cd: analog cd-rom redbook audio with internal connections to codec mixer ? mono microphone: choice of desktop or headset mic with programmable boost and gain ? speakerphone: use of system mic and speakers for telephony, dsvd, and video conferencing ? stereo line in: analog external line level source from consumer audio, video camera, etc ? video: tv tuner or video capture card with internal connections to codec mixer ? aux/synth: analog fm or wavetable synthesizer or other internal source the analog inputs connect to a stereo analog mixer as well as a stereo multiplexer. the mixer is used for playback or analog pass-through. the multiplexer is used during record. the multiplexer offers the capability to record any of the audio sources or the outgoing mix of all sources. the multiplexer implementation is more efficient than an independent mix and offers simple monitoring when a mix is recorded: what you hear is what you get. the mono and stereo mix also provides excellent echo cancellation reference signals. the tlc320ad91c supports the following full range of input options (the audio driver may maintain a consistent record input level for each multiplexer option): ? any mono or stereo source ? mono or stereo mix of all sources ? two-channel input with mono output reference (mic and stereo mix for stereo echo cancellation) 2.2 digital interface the tlc320ad91c, per the ac ? 97 specification, incorporates a 5-wire serial digital interface to a digital controller. the ac-link specifies a bidirectional, fixed rate, serial pcm digital stream. the interface handles multiple input and output audio streams, as well as control register accesses by employing a time division multiplexed (tdm) protocol. the ac-link architecture divides each audio frame into 12 outgoing and 12 incoming data streams, each with 20-bit sample resolution.
2 ? 2 the tlc320ad91c data streams, per the ac ? 97 specification, are the following: ? pcm playback has two output slots with a two-channel composite pcm output stream ? pcm record has two input slots with a two-channel composite pcm input stream ? control has two output slots with a control register write port ? status has two input slots with a control register read port ? additional data streams are defined in the ac ? 97 specification but their functionality is not implemented in the tlc320ad91c the ac ? 97 audio frame is shown in figure 2 ? 1. cmd addr cmd data pcm left pcm right rsrvd rsrvd rsrvd rsrvd rsrvd rsrvd rsrvd rsrvd tag status addr status data pcm left pcm right rsrvd rsrvd rsrvd rsrvd rsrvd rsrvd rsrvd rsrvd tag 0 1 2 3 4 5 6 7 8 9 10 11 12 data phase = 12 slots 20 bits = 240 bits tag phase = 16 bits slot sync sdout sdatin figure 2 ? 1. ac-link bidirectional audio frame (as implemented) 2.2.1 ac-link signal definitions the ac-link signals are shown in figure 2 ? 2. ac ? 97 compliant digital controller tlc320ad91c sync bitclk sdout sdatin reset figure 2 ? 2. ac-link signals
2 ? 3 the ac-link signal definitions are listed in table 2 ? 1. table 2 ? 1. ac-link signal definitions signal source description sync controller marks the beginning of each frame. sourced by the controller. occurs at a fixed rate of 48 khz unless in power-down mode. synchronous to bitclk. width of 18 bits. defines the tag phase. bitclk codec sourced by tlc320ad91c. fixed rate of 12.288 mhz. one bit is transmitted on every rising edge. one bit is captured on every falling edge. sdout controller serial bit stream sent from the controller to the codec. data and control are transmitted by the controller. sdatin codec serial bit stream sent from the codec to the controller. data and control are transmitted by the tlc320ad91c. reset controller reset signal used to bring the tlc320ad91c out of power-down mode. defines the cold tlc320ad91c reset. 2.2.2 protocol the tlc320ad91c protocol includes the following: ? the ac-link is a tdm serial interface consisting of 256 bits/frame. ? each frame is divided into two sections: a tag phase of 18 bits, and a data phase of 240 bits. ? the data phase is divided into 12 time slots with each time slot consisting of 20 bits. ? data is bidirectional with sdout transmitted by the controller, and sdatin transmitted by the codec. valid slot 1 slot 2 slot 12 00 019 019 0 19 0 cdc rdy slot 1 slot 2 slot 12 00 019 019 0 19 0 tag phase slot 1 slot 2 slot 12 sdout bitclk sync sdatin figure 2 ? 3. ac-link protocol 2.2.2.1 zero-padding the tlc320ad91c uses zero-padding which is defined as the following: ? reserved time-slots are filled with zeroes. ? unused bits within a time-slot must be filled with zeroes (e.g., 18-bit converter in a 20-bit time slot). this operation must be performed by the source (i.e., the controller for sdout, the tlc320ad91c for sdatin). ? time slots tagged as invalid must be filled with zeroes.
2 ? 4 2.2.2.2 sync the tlc320ad91c sync signal includes the following characteristics: ? sync is driven by the controller. ? sync is derived by dividing down the bitclk signal (bitclk is an input to the controller). ? sync is high for 18 bitclks at the beginning of each frame. these 18 bitclks (bits) define the tag phase. the tag phase defines the beginning of a frame. ? the tlc320ad91c synchronizes data conversion with the rising edge of sync. ? sync remains low for the next 240 bitclks. these 240 bitclks (bits) define the data phase. ? sync is sampled by tlc320ad91c at the falling edge of bitclk. ? sync transition edges are on the rising edge of bitclk. ? the controller must hold sync low during a tlc320ad91c power-down halted state. 2.2.2.3 bitclk the tlc320ad91c bitclk signal includes the following characteristics: ? bitclk is fixed at 12.288 mhz (256 sampling rate). the sampling rate is fixed at 48 khz. ? bitclk is sourced by the tlc320ad91c. ? bitclk goes low and remains low when a write to register 26h with pr4 is detected (power-down state). ? bitclk becomes active from a power-down state in response to a cold or warm tlc320ad91c reset condition. 2.2.2.4 sdout the tlc320ad91c sdout signal includes the following characteristics: ? sdout is driven by the controller. ? sdout transitions on the rising edge of bitclk. ? sdout is captured by the tlc320ad91c on the falling edge of bitclk. ? the controller must hold sdout low during an tlc320ad91c power-down halted state. 2.2.2.5 sdatin the tlc320ad91c sdatin signal includes the following characteristics: ? sdatin is driven by the tlc320ad91c. ? sdatin transitions on the rising edge of bitclk. ? sdatin is captured by the controller on the falling edge of bitclk. ? sdatin goes low and remains low when a write to register 26h with pr4 is detected (power-down state). ? sdatin becomes active from a power-down state in response to a cold or warm tlc320ad91c reset condition.
2 ? 5 2.2.3 frame contents the sdout frame contents are listed in table 2 ? 2. table 2 ? 2. sdout frame contents (driven by audio controller) slot slot name bit position name description 15 valid frame 0: indicates no valid data is in this frame 1: there is at least one tdm slot containing valid data in the frame. 0 tag 14 slot 1 valid 0: indicates no data is available in the first time slot of the data phase. slot one must be zero-padded. 1: valid data is available in the first time slot. 13 ? 3 slot x valid 0: no valid data is in slot x of the data phase. the corresponding slot must be zero-padded. 1: valid data is in slot x 2 ? 0 zero pad reserved. must be zeroes. 19 read/write 0: write to the addressed register 1: read from the addressed register 1 command address 18 ? 12 register index these seven bits are used to access the control registers. only the even numbers are used. a total of 64 registers are defined. odd numbered register accesses map to the preceding even boundary. 11 ? 0 zero pad reserved. must be zeroes. 2 command data 19 ? 4 register data if the current command operation is a write (see bit 19 of slot one) then these bits contain the data to be written. these bits must be zero-padded if the current operation is a read. 3 ? 0 zero pad reserved. must be zeroes. 3 pcm left playback 19 ? 4 pcm data 18-bit audio data. if the resolution is less than 18 bits, then the data must be right-justified and the lsbs must be zero-padded. 3 ? 0 zero pad these bits must be zeroes. 4 pcm right playback 19 ? 4 pcm data 18-bit audio data. if the resolution is less than 18 bits, then the data must be right-justified and the lsbs must be zero-padded. y 3 ? 0 zero pad these bits must be zeroes. 5 ? 12 reserved zero pad reserved. these bits must be zeroes. note that slot five is the optional modem line codec.
2 ? 6 the sdatin frame contents are listed in table 2 ? 3. table 2 ? 3. sdatin frame contents slot slot name bit position name description 15 codec ready 0: indicates the tlc320ad91c codec is not ready. 1: indicates the tlc320ad91c control and status registers are available and the ac-link is operational. the audio controller can then probe further to determine when other sections become available. 0 tag 14 slot 1 valid 0: indicates no data is available in the first time slot of the data phase. slot one must be zero-padded. 1: valid data is available in the first time slot if the codec is ready. 13 ? 3 slot x valid 0: no valid data is in slot x of the data phase. the corresponding slot must be zero-padded. 1: valid data is in slot x if the codec is ready. 2 ? 0 zero pad reserved. must be zeroes. 19 zero pad reserved. must be zero. 1 status address 18 ? 12 register index these seven bits are used to echo the control register address. the data appears in the next slot (slot two). these bits must be zero-padded if this slot is flagged invalid during the tag phase. 11 ? 0 zero pad reserved. must be zeroes. 2 status data 19 ? 4 register data contents of the register addressed by slot one (status address). these bits must be zero-padded if this slot is flagged invalid during the tag phase. 3 ? 0 zero pad these bits are zeroes. 3 pcm left record 19 ? 4 pcm data 18-bit audio data. 3 pcm left record 3 ? 0 zero pad these bits must be zeroes. 4 pcm right record 19 ? 4 pcm data 18-bit audio data. 4 pcm right record 3 ? 0 zero pad these bits are zeroes. 5 ? 12 reserved zero pad reserved. these bits must be zeroes. note that slot five is the optional modem line codec, and slot six is the optional microphone adc record data.
2 ? 7 2.2.4 ac-link low-power mode the tlc320ad91c implementation of the ac-link can be placed in a low-power mode (see section 2.7, power-down management ). when the tlc320ad91c power down register (26h) is programmed to the appropriate value, both bitclk and sdatin are brought to and held at low-voltage logic levels. as shown in figure 2 ? 4, bitclk and sdatin are transmitted low immediately following the decode of the write to the power down register (26h) with pr4. when the digital controller driver is at the point where it is ready to program the tlc320ad91c into its low-power mode, slots one and two are assumed to be the only valid stream in the audio output frame. (at this point, all sources of audio input are assumed to have also been neutralized.) slot 12 prev. frame tag write to 00 26 data pr4 ???? ???? slot 12 prev. frame tag sync bitclk (not to scale) sdout sdatin figure 2 ? 4. tlc320ad91c power-down mode timing the digital controller must also drive sync and sdout low after programming the tlc320ad91c to this low-power halted mode. once the tlc320ad91c has been instructed to halt bitclk, a special wake-up protocol must be used to bring the ac-link to the active mode since normal audio output and input frames cannot be communicated in the absence of bitclk. the ac-link can be made active again by means of a warm reset or a cold reset. see section 2.5, resetting the tlc320ad91c for details on the procedure. in summary, a warm reset is accomplished by asserting sync in the absence of bitclk. the tlc320ad91c responds according to the protocol. a warm reset retains the values programmed into the registers. a cold reset is accomplished by asserting reset . again, the tlc320ad91c responds according to the protocol. a cold reset sets all register values to their default values. note that for both cases of a reset, the signals reset and sync are treated as asynchronous inputs.
2 ? 8 2.3 software interface the register indexes and usage are shown in table 2 ? 4. all registers not shown are assumed to be reserved. table 2 ? 4. tlc320ad91c register definitions index name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 00h reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000h 02h play master volume stereo mute 0 ml5 ? ml4 ml3 ml2 ml1 ml0 0 0 mr5 ? mr4 mr3 mr2 mr1 mr0 8000h 04h ? headphone volume 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000h 06h play master volume mono mute 0 0 0 0 0 0 0 0 0 mm5 ? mm4 mm3 mm2 mm1 mm0 8000h 08h ? master tone (not used) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000h 0ah pcbeep volume mute 0 0 0 0 0 0 0 0 0 0 pv3 pv2 pv1 pv0 0 8000h 0ch phone volume mute 0 0 0 0 0 0 0 0 0 gn5 ? gn4 gn3 gn2 gn1 gn0 8008h 0eh mic volume mute 0 0 0 0 0 0 0 0 20db gn5 ? gn4 gn3 gn2 gn1 gn0 8008h 10h line in volume mute 0 0 gl4 gl3 gl2 gl1 gl0 0 0 0 gr4 gr3 gr2 gr1 gr0 8808h 12h cd volume mute 0 0 gl4 gl3 gl2 gl1 gl0 0 0 0 gr4 gr3 gr2 gr1 gr0 8808h 14h video volume mute 0 0 gl4 gl3 gl2 gl1 gl0 0 0 0 gr4 gr3 gr2 gr1 gr0 8808h 16h aux volume mute 0 0 gl4 gl3 gl2 gl1 gl0 0 0 0 gr4 gr3 gr2 gr1 gr0 8808h 18h pcm out volume mute 0 0 gl4 gl3 gl2 gl1 gl0 0 0 0 gr4 gr3 gr2 gr1 gr0 8808h ? optional ac ? 97 registers whose functionality are not implemented on the tlc320ad91c. these registers can be written to, but reads always re turn zeroes. ? special function volume settings. if bit is set, then the 5 volume bits implemented are set to all ones. note: all registers and all bits in all registers must have read back capabilities (be readable) to facilitate testing.
2 ? 9 table 2 ? 4. tlc320ad91c register definitions (continued) index name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 1ah record select control 0 0 0 0 0 sl2 sl1 sl0 0 0 0 0 0 sr2 sr1 sr0 0000h 1ch record gain mute 0 0 0 gl3 gl2 gl1 gl0 0 0 0 0 gr3 gr2 gr1 gr0 8000h 1eh ? record gain mic 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000h 20h general purpose 0 st 3d 1d 0 0 mix ms lpbk 0 0 0 0 0 0 0 0000h 22h ? 3d control 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000h 24h ? modem rate (not used) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000h 26h power- down control/ status pr7 pr6 pr5 pr4 pr3 pr2 pr1 pr0 0 0 0 mdm ref anl dac adc na 28h ? 59h reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5ah ? 7ah vendor reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000h 7ch vendor id1 f7 f6 f5 f4 f3 f2 f1 f0 s7 s6 s5 s4 s3 s2 s1 s0 5458h 7eh vendor id2 t7 t6 t5 t4 t3 t2 t1 t0 rev7 rev6 rev5 rev4 rev3 rev2 rev1 rev0 0000h ? optional ac ? 97 registers whose functionality are not implemented on the tlc320ad91c. these registers can be written to, but reads always re turn zeroes. ? special function volume settings. if bit is set, then the 5 volume bits implemented are set to all ones. note: all registers and all bits in all registers must have read back capabilities (be readable) to facilitate testing.
2 ? 10 2.3.1 reset register (index 00h) a write of any value to the reset register performs a register reset, which causes all of the registers to revert to their default values. a read of this register returns the id code of the tlc320ad91c and the type of 3d enhancement, if installed. both dacs operate at 18-bit resolution, and both adcs operate at 18-bit resolution. the id decodes the capabilities of the tlc320ad91c based on the definitions listed in table 2 ? 5. table 2 ? 5. reset register id bit definitions all bits = 0 function id0 dedicated mic pcm channel id1 modem line codec support id2 bass and treble control id3 simulated stereo (mono to stereo) id4 headphone out support id5 loudness (bass boost) support id6 18-bit dac resolution id7 20-bit dac resolution id8 18-bit adc resolution id9 20-bit adc resolution 2.3.2 play master volume stereo and mono registers (index 02h and 06h) the play master volume registers manage output signal volumes. register 02h controls the stereo master volume (both right and left channels). register 06h controls the mono volume output. each step corresponds to 1.5 db. ml5 through ml0 is for the left channel level. mr5 through mr0 is for the right channel level. mm5 through mm0 is for the mono out channel. the msb is the mute bit and is supported in the tlc320ad91c. when this bit is set to 1, the level for that channel is set at maximum attenuation. the default value of these registers is 8000h (1000 0000 0000 0000) which corresponds to 0-db attenuation with mute on. the play master volume register definitions are listed in table 2 ? 6. table 2 ? 6. play master volume register definitions mute mx5 ? mx0 function 00 0000 0-db attenuation 0 ... ... 01 1111 46.5-db attenuation 1 xx xxxx maximum attenuation (mute) 2.3.3 pcbeep volume register (index 0ah) the pcbeep volume register controls the level of the pcbeep input. each step corresponds to 3 db of attenuation. the msb of the register is the mute bit. when this bit is set to 1, the level for the channel is set at maximum attenuation. note: power-on self-test (post) codes need to be heard by the user when a hardware problem with the pc exists, even when the tlc320ad91c is in a reset state. therefore, pcbeep is routed to the left and right line outputs (a high-impedance path to the outputs is used with no attenuation).
2 ? 11 the default value of this register is 8000h which corresponds to maximum attenuation with mute on. the pcbeep register definitions are listed in table 2 ? 7. table 2 ? 7. pcbeep register definitions mute pv3 ? pv0 function 0000 0-db attenuation 0 ... ... 1111 45-db attenuation 1 xxxx maximum attenuation (mute) 2.3.4 analog mixer input gain registers (index 0ch ? 18h) the analog mixer input gain registers (phone volume, mic volume, line in volume, cd volume, video volume, aux volume, pcm out volume) control the gain and attenuation for each of the analog inputs except pcbeep. each step corresponds to approximately 1.5 db. the msb of each register is the mute bit. when this bit is set to 1, the level for that channel is set at maximum attenuation. register 0eh (mic volume register) has an extra bit for a 20-db boost. when bit d6 is set to 1, the 20-db boost is on. the default value of this register is 8008h which corresponds to 0-db gain with mute on. the default value for the mono (phone volume, mic volume) registers is 8008h which corresponds to 0-db gain with mute on. the default value for the stereo registers is 8808h which corresponds to 0-db gain with mute on. the analog mixer input gain register definitions are listed in table 2 ? 8. table 2 ? 8. analog mixer input gain register definitions mute gx4 ? gx0 function 0 0000 12-db gain ... ... 0 0 1000 0-db gain ... ... 1 1111 ? 34.5-db gain 1 x xxxx maximum attenuation (mute) 2.3.5 record select control register (index 1ah) the record select control registers are used to select the record source, independently, for the right and left channels. see tables 2 ? 9 and 2 ? 10 for the legend. the default value of this register is 0000h which corresponds to mic_in. the record select control register definitions are listed in tables 2 ? 9 and 2 ? 10. table 2 ? 9. right record select control register definitions sr2 ? sr0 right record source 000 mic_in 001 cdr 010 video_r 011 auxr 100 liner 101 stereo mix (r) 110 mono mix (r) 111 phone
2 ? 12 table 2 ? 10. left record select control register definitions sl2 ? sl0 left record source 000 mic_in 001 cdl 010 video_in_l 011 auxl 100 linel 101 stereo mix (l) 110 mono mix (l) 111 phone 2.3.6 record gain register (index 1ch) the record gain register is for the stereo input. each step corresponds to 1.5 db with 22.5 db corresponding to 0f0fh. the msb of the register is the mute bit. when this bit is set to 1, the level for that channel is set to maximum attenuation. the default value of this register is 8000h which represents 0-db gain with mute on. the record gain register definitions are listed in tables 2 ? 11. table 2 ? 11. record gain register definitions mute gx3 ? gx0 function 1111 22.5-db gain 0 ... ... 0000 0-db gain 1 xxxx maximum attenuation (mute) 2.3.7 general-purpose register (index 20h) the general-purpose register is used to control several miscellaneous functions of the tlc320ad91c: microphone output select, microphone select, and loopback. this register should be read before writing to generate a mask for only the bit(s) that need to be changed. the default value of this register is 0000h. the general-purpose register definitions are listed in table 2 ? 12. table 2 ? 12. general-purpose register definitions bit function mix mono select. 0 = mix, 1 = mic ms mic select. 0 = mic1, 1 = mic2 lpbk adc/dac loopback mode. 0: off 1: enables loopback of the adc output to the dac input without involving the ac-link thus allowing for full system performance measurements. 2.3.8 power-down control/status register (index 26h) the power-down control/status register is a read/write register used to program power-down states and monitor subsystem readiness. the lower half of this register is read-only status with a one indicating that the subsection is ready. ready is defined as the subsection that is able to perform in its nominal state. when this register is written, the bit values received on the ac-link have no effect on read-only bits 0 ? 7. when the ac-link codec ready indicator bit (sdatin, slot 0, bit 15) is a one, the ac-link and tlc320ad91c control and status registers are in a fully operational state. the digital controller must further probe this power-down control/status register to determine which subsections, if any, are ready. the power-down control/status register bits d0 ? d3 definitions are listed in table 2 ? 13.
2 ? 13 table 2 ? 13. power-down control/status register bits d0 ? d3 definitions bit function ref v ref is up to nominal level anl analog mixers, etc. ready dac dac section ready adc adc section ready the power-down modes include the following: ? the first three bits (pr0 ? pr2) are to be used individually rather than in combination with each other. ? the last bit, pr3 can be used with pr2 or by itself. ? pr0 and pr1 control the pcm adcs and dacs only. the power-down control/status register bits d8 ? d13 definitions are listed in table 2 ? 14. table 2 ? 14. power-down control/status register bits d8 ? d13 definitions bit function (see note 1) pr0 pcm in adcs and input mux power down pr1 pcm out dacs power down pr2 analog mixer power down (v ref on) pr3 analog mixer power down (v ref off) pr4 digital interface (ac-link) power down (external clock off) pr5 internal clock disabled note 1: pr6 and pr7 are specified in the ac ? 97 specification, but are not implemented in tlc320ad91c. these bits are read back as zeros. 2.3.9 reserved registers (index 28h ? 59h) these registers are reserved. write operations should not be performed to these registers. 2.3.10 vendor reserved registers (index 5ah ? 7ah) the vendor reserved registers are reserved for future use and are vendor specific. the tlc320ad91c register positions are allocated in the architecture but all bits are permanently set to zero. a write operation to any of the vendor reserved registers has no effect. a read operation of any of these registers, except for index 5ah, produces all zero values. 2.3.11 vendor id registers (index 7ch ? 7eh) the vendor id registers are for specific vendor identification, if so desired. the id method is the microsoft plug and play ? vendor id code with f7 ? f0 containing the first character of that id, s7 ? s0 containing the second id character, and t7 ? t0 containing the third id character. these three characters are ascii encoded. the rev7 ? rev0 field is for the vendor revision number. register 7ch is hard coded with 5458h and register 7eh is hard coded with 4e20h. only these values are read from these registers. plug and play is a trademark of microsoft corporation.
2 ? 14 2.4 clocking the tlc320ad91c codec derives its clock from an external 24.576-mhz crystal. the codec drives a buffered and divided down (1/2) clock to the digital controller over the ac-link on bit_clk. the frequency of this clock is 12.288 mhz. (an external oscillator can be used; however, a crystal may yield more stable operation.) see figure 2 ? 5 and figure 2 ? 6 for the clock connection options. 22 pf 22 pf xtlin xtlout dv ss1 figure 2 ? 5. crystal configuration 22 pf xtlin xtlout dv ss1 320 k ? oscillator output figure 2 ? 6. external oscillator configuration if an external oscillator is used, it must be filtered with a 22-pf capacitor. clock jitter at the data converters (dacs and adcs) is a fundamental impediment to high-quality performance. the internally generated clock provides the tlc320ad91c with a clean clock that is independent of the physical proximity of the digital controller. the beginning of all audio sample packets or audio frames transferred over the ac-link are synchronized to the rising edge of the sync signal. sync is driven by the controller. the controller receives the bitclk input and generates sync by dividing bitclk by 256 and applying conditioning to tailor the duty cycle. the result is a 48-khz sample rate sync signal whose period defines an audio frame. data is transferred out on every rising edge of bitclk and subsequently sampled on the receiving side of the ac-link on each immediately falling edge of bitclk. the audio data stream cannot be paused in record or playback since the codec does not contain data buffering capabilities.
2 ? 15 2.5 resetting the tlc320ad91c the three types of tlc320ad91c resets include the following: ? a cold reset where all tlc320ad91c logic (registers included) is initialized to the default state. this reset is accomplished by asserting reset . ? a warm reset where the contents of the tlc320ad91c register set are left unaltered. this reset is accomplished by asserting sync during an ac-link power-down state. ? a register reset which only initializes the tlc320ad91c registers to their default states. see section 2.3, software interface , register 0h. after signaling a reset to the tlc320ad91c, the digital controller should not attempt to play or capture audio data until it has sampled a codec ready indication from the tlc320ad91c. 2.5.1 cold reset a cold reset is achieved by asserting reset for 1 s. by driving reset low, bit_clk and sdata_out are activated, or reactivated, and all tlc320ad91c control registers are initialized to default power-on reset values. reset is an asynchronous input. 2.5.2 warm reset the ac-link can be put in a low-power consumption state (see section 2.3, software interface ). in this state, all signals become inactive including bitclk, and sync. a warm tlc320ad91c reset reactivates the ac-link without altering the current tlc320ad91c register values. a warm reset is signaled by driving sync high for a minimum of 1 s in the absence of bitclk. within normal audio frames, sync is a synchronous tlc320ad91c input. however, in the absence of bitclk, sync is treated as an asynchronous input used in the generation of a warm reset to the tlc320ad91c. the tlc320ad91c does not respond with the activation of bitclk until sync has been sampled low again by the tlc320ad91c. this precludes the false detection of a new audio frame. 2.5.3 reset from test mode once either of the two test modes have been entered, the tlc320ad91c must be issued another reset with all ac-link signals low to return to the normal operating mode.
2 ? 16 2.6 microphone input programmable gain amplifier the tlc320ad91c is designed to allow most common microphones to be connected to it without the use of external preamplifiers. as shown in figure 2 ? 7, the microphone input multiplexer is followed by a buffer amplifier with 100-k ? input impedance. this configuration allows the value of the input coupling capacitors to be kept small while maintaining acceptable low frequency response characteristics. as shown in figure 2 ? 7, the reference output is designed to provide bias current for two microphones. figure 2 ? 7 shows the connection of two electret microphones to the tlc320ad91c codec. + ? m u x v ref mic1 mic2 0.1 f 0.1 f refout 2.2 k ? buffer 2.2 k ? output from mic1 tlc320ad91c output from mic2 figure 2 ? 7. microphone programmable gain amplifier with two electret microphones 2.7 power-down management the tlc320ad91c is capable of operating at reduced power when no activity is required. the state of power down is controlled by the power down register (index 26h). there are seven commands of separate power down with the addition of modem codec. the tlc320ad91c is fully static and if the clock is stopped, the register values are not lost. table 2 ? 15 lists the different power-down modes. table 2 ? 15. power-down modes bits function pr0 pcm in adcs and input mux power down pr1 pcm out dacs power down pr2 analog mixer power down (v ref on) pr3 analog mixer power down (v ref off) pr4 digital interface (ac ? 97) power down (external clock off) pr5 internal clock disabled
2 ? 17 figure 2 ? 8 illustrates one example procedure for a complete power down of the tlc320ad91c. from normal operation, sequential writes to the general-purpose register are performed to power down the tlc320ad91c one section at a time. after all of the other sections have been shut down, a final write (of pr4) can be executed to shut down the tlc320ad91c digital interface (ac-link). the device remains in sleep mode with all registers holding their static values. to wake up the tlc320ad91c, the digital controller sends a pulse on sync which issues a warm reset. this operation restarts the tlc320ad91c digital interface (resets pr4 to zero). the tlc320ad91c can also be awakened with a cold reset. a cold reset causes a loss of the register values since a cold reset sets the registers back to their default states. when a section is powered back on, the power down register (index 26h) should be read to verify that the section is ready (i.e., stable) before any operation that requires the section is attempted. normal adcs off pr0 analog off pr2 or pr3 digital i/f off pr4 shut off ac-link dacs off pr1 pr0 = 0 and adc = 1 pr1 = 0 and dac = 1 pr2 = 0 and anl = 1 warm reset pr0 = 1 pr1 = 1 pr2 = 1 pr4 = 1 default ready = 1 cold reset figure 2 ? 8. tlc320ad91c power-down/ power-up flow example figure 2 ? 9 illustrates an example procedure where all of the mixers are operational with the static volume settings contained in their associated registers. this procedure is used when a cd is played (or external line source) through the tlc320ad91c to the speakers but most of the system is in low-power mode. this procedure follows the previous procedure, except that the analog mixer is never shut down. normal adcs off pr0 digital i/f off pr4 shut off ac-link dacs off pr1 pr0 = 0 and adc = 1 pr1 = 0 and dac = 1 pr0 = 1 pr1 = 1 pr4 = 1 warm reset figure 2 ? 9. tlc320ad91c power-down/power-up flow example with analog still alive
2 ? 18 2.8 mixer functions the tlc320ad91c mixer functions are listed in table 2 ? 16. table 2 ? 16. tlc320ad91c mixer functions source source connection pcbeep pcbeep pass through from pc beeper output phone speakerphone from telephony subsystem mic1 desktop microphone from microphone jack mic2 headset microphone from headset microphone jack line external audio source from line-in jack cd audio from cd-rom drive cd audio left channel vid audio from tv tuner or video camera cable from tv or video capture card aux upgrade synth or other source internal connector sdout digital audio output from digital controller ac-link mix out mix of all sources tlc320ad91c internal connection linop stereo mix of all sources to output jack monop mic or mix for speakerphone to telephony subsystem sdatin digital audio input to digital controller ac-link
3 ? 1 3 specifications 3.1 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) ? supply voltage range, av dd (see note 1) ? 0.3 v to 7 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . supply voltage range, dv dd (see note 2) ? 0.3 v to 7 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . analog input voltage range (see note 1) av ss ? 0.3 v to av dd + 0.3 v . . . . . . . . . . . . . . digital input voltage range (see note 2) dv ss ? 0.3 v to dv dd + 0.3 v . . . . . . . . . . . . . . operating free-air temperature range, t a 0 c to 70 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature range, t stg ? 65 c to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . lead temperature from case for 10 seconds 240 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . lead temperature from case for 2 minutes 183 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . esd tolerance (see note 3) 2000 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ? stresses beyond those listed under ? absolute maximum ratings ? may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under ? recommended operating conditions ? is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. notes: 1. voltage values for maximum ratings are with respect to agnd. 2. voltage values for maximum ratings are with respect to dgnd. 3. human body model per method 3015.2 of mil ? std ? 883b. 3.2 recommended operating conditions test conditions min nom max unit analog su pp ly voltage av dd1 av dd2 (see note 4) 3.3-v interface 3 3.3 3.6 v analog supply voltage , av dd1 , av dd2 (see note 4) 5-v interface 4.5 5 5.5 v digital su pp ly voltage dv dd1 dv dd2 3.3-v interface 3 3.3 3.6 v digital supply voltage , dv dd1 , dv dd2 5-v interface 4.5 5 5.5 v power supply offset voltage, dv ss ? av ss (see note 4) ? 0.3 0 0.3 v analog supply current 28 ma digital supply current 10 ma power supply rejection 20 hz, 20 khz 46 db operating free-air temperature, t a 0 25 70 c note 4: voltages at analog inputs and outputs and v ss are with respect to the agnd terminal. 3.2.1 static digital specifications, t a = 25 c, av dd1 = av dd2 = dv dd1 = 5 v 0.5 v, dv dd2 = 3.3 v 0.3 v parameter min max unit v ih high-level input voltage 2 dv dd +0.3 v v il low-level input voltage ? 0.3 0.8 v v oh high-level output voltage (i o = ? 2 ma) 2.4 dv dd v v ol low-level output voltage (i o = 2 ma) dv ss 0.4 v input leakage current ? 10 10 a output leakage current ? 10 10 a
3 ? 2 3.3 electrical characteristics 3.3.1 analog-to-digital converter, t a = 25 c, av dd1 = av dd2 = dv dd1 = dv dd2 = 5 v 0.5 v, f s = 48 khz, gain settings at 0 db, input = 1 v rms sine wave at 1 khz parameter test conditions min typ max unit signal-to-noise ratio, a-weighted 1 input = 0.9 v rms 75 80 db full-scale input voltage 0 db, v ref = 2.5 v 1 v rms total harmonic distortion ? 3-db input 0.02 % frequency response 20 19 200 hz transition band 19 200 28 800 hz stop band 28 800 hz stop band rejection ? 74 db power supply rejection ratio 20 hz ? 20 khz 46 db 3.3.2 digital-to-analog converter, t a = 25 c, av dd1 = av dd2 = dv dd1 = dv dd2 = 5 v 0.5 v, f s = 48 khz, gain settings at 0 db parameter test conditions min typ max unit signal-to-noise ratio, a-weighted 1 input = 0.9 v rms 85 90 db full-scale output voltage 0 db, v ref = 2.5 v 1 v rms total harmonic distortion ? 6-db input 0.01 % frequency response 20 19 200 hz transition band 19 200 28 800 hz stop band 28 800 hz out-of-band rejection ? 40 db spurious tone reduction ? 100 db power supply rejection ratio 20 hz ? 20 khz 46 db
3 ? 3 3.3.3 reference specifications, t a = 25 c, av dd1 = av dd2 = dv dd1 = dv dd2 = 5 v 0.5 v, f s = 48 khz parameter test conditions min typ max unit reference voltage, input/output afilt1 2/5av dd av dd /2 3/5av dd v reference volta g e, afilt2 av dd /2 ? 100 mv av dd /2 av dd /2+ 100 mv v g, output refout buffered vafilt1 v reference voltage, mixer ref buffered vafilt1 v reference voltage, adc cap1 buffered vafilt1 v reference voltage, dac cap2 buffered vafilt1 v current, sink cap1, cap2, afilt2, ref, and refout ? 5 ma current, source cap1, cap2, ref, and refout 5 ma voltage afilt1 v dd =4v 5 5 v nom 2.5 v voltage afilt2 v dd = 4 v ? 5 . 5 v nom 1.5 v voltage, switch threshold afilt2 3.6 3.8 v impedance afilt1 75 k ?
3 ? 4 3.3.4 circuit specifications, t a = 25 c, av dd1 = av dd2 = dv dd1 = dv dd2 = 5 v 0.5 v, f s = 48 khz, for gain settings at 0 db, input = 1 v rms sine wave at 1 khz parameter test conditions min typ max unit mixer circuit v dd = 5 v signal to noise ratio cd path a-weighted 1 90 95 db signal - to - noise ratio other paths a-weighted 1 85 95 db maximum input voltage av ss 1 av dd vrms maximum output voltage linop 1 vrms total harmonic distortion 0.02 % frequency response ( 1 db) 20 20 000 hz cd inputs at any gain 10 20 30 other mixer in p uts at maximum gain 10 20 30 input impedance other mixer inputs at 0-db gain 50 100 150 k ? mic in p uts at maximum gain 10 20 30 mic inputs at 0-db gain 55 110 165 power supply rejection ratio 20 hz ? 20 khz 46 db power supply monitor and power on reset (por) por threshold voltage 1.5 2.4 2.7 v
3 ? 5 3.4 timing requirements 3.4.1 device timing requirements, t a = 25 c, av dd1 = av dd2 = dv dd1 = dv dd2 = 5 v 0.5 v, f s = 48 khz, for gain settings at 0 db, input = 1 v rms sine wave at 1 khz parameter test conditions min nom max unit clock frequencies crystal clock frequency 24.576 mhz bitclk frequency 12.288 mhz sync frequency 48 khz ac-link power down timing t d1 delay time, end of slot 2, sdatin low, to bitclk low 1 s cold reset timing t wl(rst) pulse duration, reset active low 1 s t d(rst_clk) delay time, startup, reset inactive to bitclk 162.8 ns warm reset timing t wh(sync) pulse duration, sync active high 1.3 s t d(sync_clk) delay time, sync inactive to bitclk startup 162.8 ns clock timing t cyc(clk) cycle time bitclk 81.4 ns output jitter, bitclk 600 ps t wh(clk) pulse duration, bitclk high 32.56 40.7 48.84 ns t wl(clk) pulse duration, bitclk low 32.56 40.7 48.84 ns t cyc(sync) cycle time, sync 20.8 s t wh(sync) pulse duration, sync high 1.3 s t wl(sync) pulse duration, sync low 19.5 s data setup and hold timing t su1 setup time, falling edge of bitclk 15 ns t h1 hold time, falling edge of bitclk 5 ns signal rise and fall timing t r(clk) rise time, bitclk 2 6 ns t f(clk) fall time, bitclk 2 6 ns t r(sync) rise time, sync 2 6 ns t f(sync) fall time, sync 2 6 ns t r(din) rise time, sdatin 2 6 ns t f(din) fall time, sdatin 2 6 ns t r(dout) rise time, sdout 2 6 ns t f(dout) fall time, sdout 2 6 ns
3 ? 6 3.4.2 ate test mode timing requirements, t a = 25 c, av dd = dv dd = 5 v dc, av ss = dv ss = 0 v, 50-pf external load parameter min typ max unit t su3 setup time, sdout , sync to reset (see notes 5 and 6) 15 ns t d(off) delay time, reset to sdatin, bitclk hi-z (see notes 5 and 6) 25 ns notes: 5. all ac-link signals are normally low though reset . sdout should be high prior to reset which causes the tlc320ad91c ac-link outputs to go high impedance which is suitable for ate in circuit testing. 6. the texas instruments internal test mode is entered by bringing sync high prior to reset . this mode has no effect on the tlc320ad91c ac-link output signal levels.
4 ? 1 4 parameter measurement information write to 00 26 data pr4 ????? ????? ????? sync bitclk sdout sdatin slot 1 slot 2 t d1 don ? t care figure 4 ? 1. ac-link low-power mode timing t wh(clk) t wl(clk) t cyc(clk) t wl(sync) t wh(sync) t cyc(sync) bitclk sync figure 4 ? 2. clock timing bitclk t su1 t h1 sdatin, sdout, sync figure 4 ? 3. data setup and hold timing
4 ? 2 t r(clk) t f(clk) t r(din) t f(din) t r(dout) t f(dout) t r(sync) t f(sync) bitclk sdatin sdout sync figure 4 ? 4. signal rise and fall timing t wl(rst) t d(rst_clk) reset bitclk figure 4 ? 5. cold reset timing t wh(sync) t d(sync_clk) sync bitclk figure 4 ? 6. warm reset timing t su3 t d(off) reset sdout, sync sdatin, bitclk hi-z figure 4 ? 7. ate test mode timing
5 ? 1 5 application information/system usage the system diagram in figure 5 ? 1 shows the essential components, including the tlc320ad91c, used in the design of a system. in this scenario, the tlc320ad91c operates at the fixed sample rate of 48 khz and performs digital-to-analog conversion, analog-to-digital conversion, analog input, mixing, and allows for the insertion of analog and digital signal processing (3d sound, stereo enhancement, etc). digital controller sample rate conversion sound blaster registers synthesis ac-3 directx etc. pci bus ac-link ad91 codec analog i/o adc dac analog mixer digital interface analog output game port volume up/down mute analog inputs figure 5 ? 1. system diagram the digital controller, generally connected to the pci bus, performs the following functions: ? sample rate conversion to and from 48 khz ? sound blaster compatibility ? fm synthesis ? wave table synthesis ? direct sound acceleration (optional) ? ac-3 decode the digital link is an ac ? 97 compatible bidirectional, 5-wire, serial tdm format interface designed for a dedicated point-to-point interconnect on a circuit board. 5.1 software driver support for the texas instruments tlc320ad91c stereo codec the tlc320ad91c codec is compatible with software drivers developed to conform to the ac ? 97 audio codec specification. with the use of an ac ? 97 compliant digital controller, the tlc320ad91c can perform high quality (90-db snr) sample rate conversions on a minimum of four simultaneous channels (stereo in and stereo out) and between a variety of sample rates. with the input sample rate at 48 khz, data conversion to 8, 11.025, 16, 22.05, 32, and 44.1 khz are possible. mono pcm always translates to two mono channels ( l and r) on the ac ? 97 ac-link.
5 ? 2 5.2 the texas instruments tlc320ad91c connected to an ac ? 97 compliant digital controller the tlc320ad91c communicates with an ac ? 97 compliant digital controller through the digital serial link or ac-link. in addition to all digital audio streams, command and status information is also communicated over this point-to-point serial connection. this connection is shown in figure 5 ? 2. ac ? 97 compliant digital controller tlc320ad91c sync bitclk sdout sdatin reset figure 5 ? 2. connection to an ac ? 97 digital controller 5.3 testability 5.3.1 activating the test modes the tlc320ad91c has two test modes. one mode is for ate in circuit test and the other mode is for texas instruments specific tests. the two test modes are activated according to the following: ? the tlc320ad91c enters the ate in circuit test mode if sdata_out is sampled high at the trailing edge of reset . ? the tlc320ad91c enters the texas instruments test mode when coming out of reset if sync is high. ? the tlc320ad91c enters texas instruments scan test mode when coming out of reset when both sync and sdout are held high. these cases should never occur during standard operating conditions. regardless of the test mode, the digital controller must issue a cold reset to resume normal operation of the tlc320ad91c. 5.3.2 test mode functions ? ate in circuit test mode when the tlc320ad91c is placed in the ate test mode, the tlc32ad91c digital ac-link outputs (i.e., bitclk and sdatin) are driven to a high-impedance state. this condition allows ate in circuit testing of the digital controller.
a ? 1 appendix a mechanical data pt (s-pqfp-g48) plastic quad flatpack 4040052 / c 11/96 0,13 nom 0,17 0,27 25 24 sq 12 13 36 37 6,80 7,20 1 48 5,50 typ 0,25 0,45 0,75 0,05 min sq 9,20 8,80 1,35 1,45 1,60 max gage plane seating plane 0,10 0 ? 7 0,50 m 0,08 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. falls within jedec ms-026 d. this may also be a thermally enhanced plastic package with leads conected to the die pads.
a ? 2
packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish msl peak temp (3) TLC320AD91CPT obsolete lqfp pt 48 tbd call ti call ti (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs) or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. package option addendum www.ti.com 30-mar-2005 addendum-page 1

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